1. Field of the Invention
The present invention relates to the implementation of read and writable data buses on integrated circuits; and more particularly to the implementation of programmable interconnect structures on programmable logic devices including long line read and writable data buses.
2. Description of Related Art
Field programmable gate arrays (FPGAs) comprise an integrated collection of logic blocks, programmably interconnected through a routing matrix. These blocks typically include registers, logic elements such as SRAM based look-up tables or a sea of gates, and tristate buffers for applying output data to buses. The user programs the logic block configuration and the routing matrix to produce a desired function.
The prior art FIG. 1 illustrates a typical data bus interconnect structure used in an FPGA. In FIG. 1, the data bus structure includes a conductor 10 driven by a set of tristate buffers 11, 12, 13, which have respective enable input lines 14, 15, 16, and respective data input lines 17, 18, 19. The gates of the segmentation transistors 20 and 21 are controlled by configurable storage elements 22 and 23, respectively. The conductor 10 is programmably expanded into larger sizes by turning on the segmentation transistors 20 and 21 (via the configurable storage elements 22 or 23). This prior art approach has a few shortcomings, including, for example, when several tristate buffers are enabled (turned on) simultaneously, a severe power consumption occurs on the device.
In the prior art tristate buffer configuration shown in FIG. 1, the longer the signal path down a long line, the more complicated it is to predict the delay associated with that signal. The prediction is complicated because the long line behaves like a transmission line with capacitive loading. The number of capacitors and the length of the line affect the delay of the signal on the line by a complex non-linear formula. Thus, early stage design tools for FPGA devices, must rely on relatively complicated techniques for managing the routing signals where long lines are involved.
FIG. 2 illustrates an alternative circuit for data bussing applications according to the prior art, which is also used in FPGAs. In the implementation of FIG. 2, a segment 30 of the interconnect structure is driven by a set of n-channel transistors 31, 32, 33. The gates of the n-channel transistors 31, 32, 33 receive the data input signals 34, 35, 36, respectively. If at least one input signal is high, the associated n-channel transistor turns on and pulls the signal on the segment 30 to ground. A passive pull-up device 37 is also coupled to the segment 30 to provide a logic high condition to the segment 30 when all transistors 31, 32, 33 are turned off. This passive pull-up device 37 may be a resistor (as shown), or a transistor biased in a conductive condition. Segmentation transistors 38 and 39 which are enabled by configurable storage elements 40 and 41 are also connected in the interconnect structure, in a similar manner to that of FIG. 1. This circuit does not suffer the unpredictability problem that exists with the system of FIG. 1, because of the current limiting effect of the pull-up device 37. However, there is a steady DC current consumed through the pull-up device 37. The approach of FIG. 2 also suffers the disadvantage of rapid degradation of the signal in a non-linear fashion as more bus segments are concatenated through the interconnect transistors 38 and 39. Furthermore, in order to pull up the conductor 30 with a reasonable performance, the pull-up device 37 must be sufficiently low in impedance. However, since the DC current on the segment increases with a lower impedance pull up, electromigration issues have to be considered when laying out the conductor used for the bus.
Accordingly, a need arises for a read and writable data bus structure, suitable for implementation of FPGA's and on other integrated circuit devices, which is fast, provides predictable delays, minimizes power consumption, is contention-free, and is programmably segmented into smaller buses.